Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
A flash memory is a type of memory that can be erased and reprogrammed in blocks instead of one byte at a time. A typical flash memory comprises a memory array, which includes a large number of memory cells. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The cells are usually grouped into blocks. Each of the cells within a block can be electrically programmed in a random basis by charging the floating gate. The data in a cell is determined by the presence or absence of the charge in the floating gate. The charge can be removed from the floating gate by a block erase operation.
A typical prior art block erase operation first pre-programs the memory block before an erase operation is performed. The pre-programming reduces the chances of the cells going into a depletion mode. As the cells in a flash memory device get erased, they may get erased to the point where they go into depletion and conduct current even when those cells have a gate voltage of 0 V. This affects the reading of all other cells in their respective columns. By pre-programming the memory, the cells start from a known, programmed state and are therefore less likely to go into an overerased depletion state.
The memory block is then erased. The erase operation is conducted to erase the cells to at least a minimum voltage level. The drain and source connections of the bit lines are all typically left floating as are the select gate drain transistors and the select gate source transistors. The word lines of the block to be erased are at ground potential.
An erase verify read is then performed to determine the success of the erase operation on each cell of the memory block. One such erase verify operation comprises, at least in part, comparing each cell's erase current to a sense amplifier reference current level. During this operation, all of the word lines of the block are held at one predetermined voltage (e.g., 0 V) while the selected bit lines are biased at another voltage (e.g., VCC). A pulse at a predetermined level (e.g., 0 V) is applied to the unselected bit lines. The select gate drain and source transistors are typically at 4.5 V that is typically referred to in the art as Vpass. If the verify operation fails, the erase operation is performed again. If the erase verify passes, the erase operation has been successfully completed.
If a column of cells has only one unerased cell after an erase verify, the prior art erase operation applies additional erase pulses to the entire column. This can overstress memory cells in the column that are already erased and do not require additional erase pulses. The overstressing of the cells can increase their failure rate.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an erase algorithm that reduces the overstressing of memory cells in a flash memory device.